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LTC1421/LTC1421-2.5 Hot Swap Controller
FEATURES
s s s s s s s s s
DESCRIPTION
The LTC(R)1421/LTC1421-2.5 are Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the board supply voltages can be ramped up at a programmable rate. Two high side switch drivers control the Nchannel gates for supply voltages ranging from 3V to 12V. A programmable electronic circuit breaker protects against shorts. Warning signals indicate that the circuit breaker has tripped, a power failure has occurred or that the switch drivers are turned off. The reset output can be used to generate a system reset when the power cycles or a fault occurs. The two connect inputs can be used with staggered connector pins to indicate board insertion or removal. The power-on reset input can be used to cycle the board power or clear the circuit breaker. The trip point of the ground sense comparator is set at 0.1V for LTC1421 and 2.5V for LTC1421-2.5.
Allows Safe Board Insertion and Removal from a Live Backplane System Reset and Power Good Control Outputs Programmable Electronic Circuit Breaker User Programmable Supply Voltage Power-Up Rate High Side Driver for Two External N-Channels Controls Supply Voltages from 3V to 12V Connection Inputs Detect Board Insertion or Removal Undervoltage Lockout Power-On Reset Input
APPLICATIONS
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Hot Board Insertion Electronic Circuit Breaker
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
The LTC1421/LTC1421-2.5 are available in 24-pin SO and SSOP packages.
TYPICAL APPLICATION
Q3 1/2 Si4936DY C3 0.47F VEE VDD R1 0.005 VCC
STAGGERED CONNECTOR
Q2 R2 0.025 1/2 Si4936DY Q1 MTB50N06E
D1 R3 1k
23
22
21
20
19
18
17
16 10 9 14 13 8 11 15 6 7
VCCLO SETLO GATELO VOUTLO VCCHI 2 CON2 24 AUXVCC C1 1F 4 FAULT
SETHI GATEHI VOUTHI RAMP CPON COMP - COMP + REF FB COMPOUT PWRGD RESET
C2 0.1F
R5 16k 5%
R6 20k 1%
1F
LTC1421
R7 7.15k 1% P I/O I/O RESET
FAULT POR
3 POR 1 CON1
GND 12
DISABLE 5 1 BEA VCC 13 BEB 12 GND QS3384 QuickSwitch(R)
GND
DATA BUS
1421 TA01
DATA BUS
QuickSwitch IS A REGISTERED TRADEMARK OF QUALITY SEMICONDUCTOR CORPORATION.
BACKPLANE
PC BOARD
+
R4 20k 5%
U
U
U
C5 220F
VEE - 12V 1A VDD 12V 1A VCC 5V 5A
+ +
C3 220F C4 220F
1
LTC1421/LTC1421-2.5 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW CON1 CON2 POR FAULT DISABLE PWRGD RESET REF CPON 1 2 3 4 5 6 7 8 9 24 AUXVCC 23 VCCLO 22 SETLO 21 GATELO 20 VOUTLO 19 VCCHI 18 SETHI 17 GATEHI 16 VOUTHI 15 COMPOUT 14 COMP - 13 COMP +
Supply Voltage (VCCLO, VCCHI, AUXVCC) .............. 13.2V Input Voltage (Analog Pins) ..... - 0.3V to (VCCHI + 0.3V) Input Voltage (Digital Pins) ................... - 0.3V to 13.2V Output Voltage (Digital Pins) .. - 0.3V to (VCCLO + 0.3V) Output Voltage (CPON) ......... - 13.2V to (VCCLO + 0.3V) Output Voltage (VOUTLO, VOUTHI) ........... - 0.3V to 13.2V Output Voltage (GATELO, GATEHI) ........... - 0.3V to 20V Operating Temperature Range .................... 0C to 70C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1421CG LTC1421CSW LTC1421-2.5CG LTC1421-2.5CSW
RAMP 10 FB 11 GND 12
G PACKAGE 24-LEAD PLASTIC SSOP SW PACKAGE 24-LEAD PLASTIC SO
TJMAX = 125C, JA = 100C/W (G) TJMAX = 125C, JA = 85C/W (SW)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL ICCLO ICCHI VLKO VLKH VREF VLNR VLDR IRSC VCOF VCPSR VCHST VRST PARAMETER VCCLO Supply Current VCCHI Supply Current Undervoltage Lockout Undervoltage Lockout Hysteresis Reference Output Voltage Reference Line Regulation Reference Load Regulation Reference Short-Circuit Current Comparator Offset Voltage Comparator Power Supply Rejection Comparator Hysteresis Reset Voltage Threshold (VOUTLO) DC Characteristics
VCCHI = 12V, VCCLO = 5V, TA = 25C unless otherwise noted (Note 2).
MIN
q q
CONDITIONS CON1 = CON2 = GND, POR = VCCLO CON1 = CON2 = GND, POR = VCCLO VCCLO and VCCHI VCCLO and VCCHI No Load 3V VCCLO 12V, No Load IO = 0mA to - 5mA, Sourcing Only VREF = 0V 0V VCM (VCCLO - 1.3V) 0V VCM (VCCLO - 1.3V), 3V VCCLO 12V 0V VCM (VCCLO - 1.3V) FB = VOUTLO FB = Floating FB = GND FB = VOUTLO FB = Floating FB = GND 0V VFB VCCLO VCB = (VCCLO - VSETLO) or VCB = (VCCHI - VSETHI) LTC1421 (Note 3) LTC1421-2.5 (Note 4)
q q q q q q q q q
TYP 1.5 0.6
MAX 3 1 2.60 1.244 8 3 10 1
UNITS mA mA V mV V mV mV mA mV mV/V mV V V V mV mV mV k
2.28 1.220
2.45 100 1.232 4 1 - 45
7 2.80 4.50 5.75 2.90 4.65 5.88 7 12 15 95 40 50 0.1 2.5 60 3.00 4.75 6.01
VRHST
Reset Threshold Hysteresis (VOUTLO)
RFB VCB VTRIP
FB Pin Input Resistance Circuit Breaker Trip Voltage Output Voltage for Re-Power-Up
2
U
mV V V
W
U
U
WW
W
LTC1421/LTC1421-2.5
ELECTRICAL CHARACTERISTICS
SYMBOL IRAMP ICP VGATEHI VAUXVCC VIL VIH IIN VOL PARAMETER RAMP Pin Output Current Charge Pump Output Current GATEHI N-Channel Gate Drive Auxiliary VCC Output Voltage Input Low Voltage Input High Voltage Input Current Output Low Voltage
VCCHI = 12V, VCCLO = 5V, TA = 25C unless otherwise noted (Note 2).
MIN
q
CONDITIONS Charge Pump On, VRAMP = 0.4V Charge Pump On, GATEHI = 0V GATELO = 0V VGATEHI - VOUTHI VGATELO - VOUTLO VCCLO = 5V, Unloaded CON1, CON2, POR CON1, CON2, POR CON1, CON2, POR = GND RESET, COMPOUT, PWRGD, DISABLE, FAULT, IO = 3mA CPON, IO = 3mA DISABLE, IO = - 3mA CPON, IO = - 1mA RESET, PWRGD, FAULT = GND Figure 1, CL = 15pF Figure 1, RL = 10k to VCCLO, CL = 15pF
q q q q q q q q q
TYP 17 - 600 - 300
MAX 23
UNITS A A A
11
6 10 4.5
16 16 0.8
V V V V V A V V V V
VGATELO GATELO N-Channel Gate Drive
2 - 30 - 60 - 90 0.4 1.45 4 3.4 - 15 15 160 140 160 140 15 20 200 200 200 200 20 32 50 50 20 20 20 30 240 280 240 280 30
VOH IPU t1 t2 t3 t4 t5 t6 t7 t9 t10 t11 tCHL tCLH
Output High Voltage Logic Output Pull-Up Current CON1 or CON2 to CPON PWRGD to RESET PWRGD to DISABLE POR to CPON PWRGD to RESET POR to CPON CON1 or CON2 to CPON Short-Circuit Detect to FAULT Short-Circuit Detect to CPON POR to FAULT Comparator High to Low Comparator Low to High
A ms ms ms ms ms ms s ns ns s s ns 0.5 1.5 s s
AC CHARACTERISTICS
Figure 1, CL = 15pF
q
Figure 1, CL = 15pF Figure 1, RL = 10k to VCCLO, CL = 15pF Figure 1, CL = 15pF Figure 1, CL = 15pF Figure 1, RL = 10k to VCCLO, CL = 15pF VCCLO - SETLO = 0mV to 100mV Figure 2, CL = 15pF VCCLO - SETLO = 0mV to 100mV Figure 2, RL = 10k to VCCLO, CL = 15pF COMP - = 1.232V, 10mV Overdrive RL = 10k to VCCLO, CL = 15pF
q
q q
0.25 1
COMP - = 1.232V, 10mV Overdrive RL = 10k to VCCLO, CL = 15pF
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified.
Note 3: After power-on reset, the VOUTLO and VOUTHI have to drop below the VTRIP point before the charge pump is restarted. Note 4: After power-on reset, the VOUTLO has to drop below the VTRIP point before the charge pump is restarted.
3
LTC1421/LTC1421-2.5 TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage vs Temperature
1.238 1.236 REFERENCE VOLTAGE (V) 1.234 1.232 1.230 1.228 1.226 1.224 - 50 - 25 VCCLO = 5V VCCHI = 12V 24 23 GATE VOLTAGE (V) 22 GATEHI 21 20 19 GATELO 18 17 - 50 - 25 VCCLO = 5V VCCHI = 12V
REFERENCE VOLTAGE (V)
50 25 75 0 TEMPERATURE (C)
GATELO Voltage vs VCCLO Voltage
26 24 GATELO VOLTAGE (V) 22 20 18 16 14 12 0 2 8 6 10 4 VCCLO VOLTAGE (V) 12 14 GATEHI VOLTAGE (V) VCCHI = 12V 26 24 22 20 18 16 14 12
ICCLO SUPPLY CURRENT (A)
ICCHI Supply Current vs Temperature
555 550 ICCHI SUPPLY CURRENT (A) 545 VCCLO = 5V VCCHI = 12V 600 500 400 300
VOLTAGE (mV)
540 535 530 525 520 - 50 - 25
COMPOUT PWRGD RESET FAULT
CPON VOLTAGE (V)
50 25 75 0 TEMPERATURE (C)
4
UW
100
1421 G01 1421 G04
Gate Voltage vs Temperature
1.245
Reference Voltage vs Source Current
VCCLO = 5V VCCHI = 12V 1.240
1.235
1.230
1.225
125
50 25 75 0 TEMPERATURE (C)
100
125
1.220
0
2
6 8 4 SOURCE CURRENT (mA)
10
1421 G03
1421 G02
GATEHI Voltage vs VCCHI Voltage
VCCLO = 5V 1500
ICCLO Supply Current vs Temperature
VCCLO = 5V VCCHI = 12V
1400
1300
0
2
8 6 10 4 VCCHI VOLTAGE (V)
12
14
1200 - 50 - 25
50 25 75 0 TEMPERATURE (C)
100
125
1421 G05
1421 G06
VOL vs ISINK
2.5 VCCLO = 5V VCCHI = 12V 2.0
CPON Voltage vs Sink Current (Charge Pump Off)
VCCLO = 5V VCCHI = 12V
1.5
1.0
200 100 0 0 2 4 6 SINK CURRENT (mA) 8 10
1421 G08
0.5
100
125
0
0
0.5
1.0 1.5 2.0 SINK CURRENT (mA)
2.5
3.0
1421 G09
1421 G07
LTC1421/LTC1421-2.5 TYPICAL PERFORMANCE CHARACTERISTICS
CPON Voltage vs Source Current (Charge Pump On)
5 VCCLO = 5V VCCHI = 12V 4 CPON VOLTAGE (V) ICCLO SUPPLY CURRENT (mA) 7 VCCHI = 12V 6 5 4 3 2 1 0 0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 SOURCE CURRENT (mA) - 3.0 0 2 8 6 10 4 VCCLO VOLTAGE (V) 12 14
3
2
1
0
PIN FUNCTIONS
CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO. Together with CON2, it is used to indicate board connection. The pin must be tied to ground on the host side of the connector. When using staggered connector pins, CON1 and CON2 must be the shortest and must be placed at opposite corners of the connector. Board insertion is assumed after CON1 and CON2 are both held low for 20ms after power-up. CON2 (Pin 2): TTL Level Input with a Pull-Up to VCCLO. Together with CON1 it is used to indicate board connection. POR (Pin 3): TTL Level Input with a Pull-Up to VCCLO. When the pin is pulled low for at least 20ms, a hard reset is generated. Both VOUTLO and VOUTHI will turn off at a controlled rate. A power-up sequence will not start until the POR pin is pulled high. If POR is pulled high before VOUTLO and VOUTHI are fully discharged, a power-up sequence will not begin until the voltage at VOUTLO and VOUTHI are below VTRIP. The electronic circuit breaker will be reset by pulling POR low. FAULT (Pin 4): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low when an overcurrent fault is detected at VOUTLO or VOUTHI. DISABLE (Pin 5): CMOS Output. The signal is used to disable the board's data bus during insertion or removal. PWRGD (Pin 6): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low immediately after VOUTLO falls below its reset threshold voltage. The pin is pulled high immediately after VOUTLO rises above its reset threshold voltage. RESET (Pin 7): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low when a reset condition is detected. A reset will be generated when any of the following conditions are met: Either CON1 or CON2 is high, POR is pulled low, VCCLO or VCCHI are below their respective undervoltage lockout thresholds, PWRGD goes low or an overcurrent fault is detected at VOUTLO or VOUTHI. RESET will go high 200ms after PWRGD goes high. On power failure, RESET will go low 32s after PWRGD goes low. REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V 1%. The reference can source up to 5mA of current. A 1F bypass capacitor is recommended. CPON (Pin 9): CMOS Output That Can Be Pulled Below Ground. CPON is pulled high when the internal charge pumps for GATELO and GATEHI are turned on. CPON is pulled low when the charge pumps are turned off. The pin can be used to control an external MOSFET for a - 5V to - 12V supply.
UW
ICCLO Supply Current vs VCCLO Voltage
1421 G10
1421 G11
U
U
U
5
LTC1421/LTC1421-2.5
PIN FUNCTIONS
RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By connecting an external capacitor between the RAMP and GATEHI, a positive linear voltage ramp on GATEHI and GATELO is generated on power-up with a slope equal to 20A/CRAMP. FB (Pin 11): Analog Feedback Input. FB is used to set the reset threshold voltage on VCCLO. For a 5V supply leave FB floating. For a 3.3V supply, short FB to VCCLO. GND (Pin 12): Ground COMP + (Pin 13): Noninverting Comparator Input. COMP - (Pin 14): Inverting Comparator Input. COMPOUT (Pin 15): Open Drain Comparator Output. VOUTHI (Pin 16): High Supply Voltage Output. This must be the higher of the two supply voltage outputs. GATEHI (Pin 17): The High Side Gate Drive for the High Supply N-Channel. An internal charge pump guarantees at least 6V of gate drive. The slope of the voltage rise at GATEHI is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips, GATEHI is immediately pulled to GND. SETHI (Pin 18): The Circuit Breaker Set Pin for the High Supply. With a sense resistor placed in the supply path between VCCHI and SETHI, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20s. To disable the circuit breaker, VCCHI and SETHI should be shorted together. VCCHI (Pin 19): The Positive Supply Input. This must be the higher of the two input supply voltages. An undervoltage lockout circuit disables the chip until the voltage at VCCHI is greater than 2.45V. VOUTLO (Pin 20): Low Supply Voltage Output. This must be the lower of the two supply voltage outputs. GATELO (Pin 21): The High Side Gate Drive for the Low Supply N-Channel Pass Transistor. An internal charge pump guarantees at least 10V of gate drive. The slope of the voltage rise at GATELO is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips GATELO is immediately pulled to GND. SETLO (Pin 22): The Circuit Breaker Set Pin for the Low Supply. With a sense resistor placed in the supply path between VCCLO and SETLO, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20s. To disable the circuit breaker, VCCLO and SETLO should be shorted together. VCCLO (Pin 23): The Positive Supply Input. VCCLO must be equal to or lower voltage than VCCHI. An undervoltage lockout circuit disables the chip until the voltage at VCCLO is greater than 2.45V. AUXVCC (Pin 24): The supply input for the GATELO and GATEHI discharge circuitry. Connect a 1F capacitor to ground. AUXVCC is powered from VCCLO via an internal Schottky diode and series resistor.
6
U
U
U
LTC1421/LTC1421-2.5
BLOCK DIAGRAM
VCC 24 AUXVCC
VCC UNDERVOLTAGE LOCKOUT CP4
9
CPON
VCC
20A 4 FAULT
1 2 3
CON1 20A CON2 POR RESET TIMING RESET 7
5 12
DISABLE GND
SWITCHI G TI E WAVEFOR S
t1 CON1 t2 t5 t7
VCCLO - SETLO t9 t5 t11 t2
CON2 CPON PWRGD
RESET DISABLE POR t3 t4 t6
Figure 1. Nominal Operation Switching Waveforms
W
W
23 VCCLO 22 SETLO 19 VCCHI 18 SETHI 21 GATELO 10 RAMP 17 16 20 VOUTLO GATEHI VOUTHI 50mV
+ -
50mV
+ -
AUXVCC
CHARGE PUMP N2 N1
CP1
CP2
CP3
+ + - + - - +
1.232V REFERENCE VTRIP
73.5k
71.5k 26.7k
FB
11
REF VCC
8
20A VCC DIGITAL CONTROL
PWRGD
6
+ -
CP5 COMPOUT 15
COMP - COMP +
14 13
1421 BD
W
U
FAULT CPON PWRGD
RESET POR
1421 F01
1421 F02
t10
t6
Figure 2. Fault Detection Switching
7
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. The transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. At the same time, the system data bus can be disrupted when the board's data pins make or break connection. The LTC1421 is designed to turn a board's supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides a disable signal for the board's data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board. Power Supply Ramping The power supplies on a board are controlled by placing external N-channel pass transistors in the power path (Figure 3). R1 and R2 provide current fault detection. By ramping the gate of the pass transistor up at a controlled rate, the transient surge current (I = C * dV/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection.
R2 12V R1 5V 23 22 21 20 19 18 17 16 Q1 Q2 12V VOUTHI
+
C3
VCCLO SETLO GATELO VOUTLO VCCHI SETHI GATEHI VOUTHI 1 2 CON1 CON2
1421 F03
LTC1421
RAMP
B R5 16k 5% 9 CPON LTC1421
5V CPON -12V 0V B -12V 0V VEE -12V ~1ms ~1ms
Figure 3: Supply Control Circuitry
When power is first applied to the chip, the gates of both N-channels, GATELO and GATEHI are pulled low. After the connection sense pins, CON1 and CON2 are both held low for at least 20ms, a 20A reference current is connected from the RAMP pin to GND. The voltage at GATEHI begins to rise with a slope equal to 20A/CRAMP (Figure 4), where CRAMP is an external capacitor connected between the
Figure 5. Negative Supply Control
8
+
10
U
+
W
U
U
SLOPE = 20A/CRAMP
5V
VOUTLO
t1
t2
1421 F4a
Figure 4. Supplies Turning On
RAMP and GATEHI pins. The voltage at the GATELO pin is clamped one Schottky diode drop below GATEHI. The ramp time for each supply is equal to: t = (VCC) (CRAMP)/20A. During power down the gates are actively pulled down by two internal NFETs. A negative supply voltage can be controlled using the CPON pin as shown in Figure 5. When the board makes connection, the transistor Q3 is turned off because it's gate is pulled low to -12V by R4. CPON is also pulled to -12V. When the charge pump is turned on, CPON is pulled to VCCLO and the gate of Q3 will ramp up with a time constant determined by R4, R5 and C2. When the charge pump is turned off, CPON goes into a high impedance state, the gate of Q3 is discharged to VEE with a time constant determined by R4 and C2, and Q3 turns off.
-12V FROM CONNECTOR Q3 1/2 MMDF3N0HD C2 0.047F R4 20k 5% C5 220F VEE -12V 1A
VOUTHI
VOUTLO C4
CRAMP
1421 F05
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
PWRGD and RESET The LTC1421 uses a 1.232V bandgap reference, internal resistive divider and a precision voltage comparator to monitor VOUTLO (Figure 6). The reset threshold voltage for VOUTLO is determined by the FB pin connection as summarized in Table 1.
VCCLO VOUTLO
20A PWRGD VCCLO
COMP1
73.5k 71.5k
-
26.7k
+
20A RESET RESET TIMING 1.232V REF
1421 F06
Figure 6. Supply Monitor Block Diagram Table 1
FEEDBACK PIN Floating VOUTLO GND VOUTLO RESET VOLTAGE 4.65V 2.90V 5.88V
When the VOUTLO voltage rises above its reset threshold voltage, the comparator output goes low, and PWRGD is immediately pulled high to VCCLO by a weak pull-up current source or external resistor (Figure 7, time points 1 and 4). After a 200ms delay, RESET is pulled high. The weak pull-up current source to VCCLO on PWRGD and RESET have a series diode so the pins can be pulled above VCCLO by an external pull-up resistor without forcing current back into VCCLO.
1 V2 VOUTLO 2 V1 V2 3 V1 V2 4 V2 5 V1
PWRGD 64s RESET 200ms < 200ms < 64s 200ms
1421 F07
Figure 7. Power Monitor Waveforms
U
W
U
U
When VOUTLO drops below its reset threshold, the comparator output goes high, and PWRGD is immediately pulled low (time point 2). After a 32s delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be used as an early warning that a reset is about to occur. If the PWRGD signal is used as a interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. If VOUTLO rises above the reset threshold for less than 200ms, the PWRGD output will trip, but the RESET output is not affected (time point 3). If VOUTLO drops below the reset threshold for less than 32s, the PWRGD output will trip, but again the RESET output will not be affected (time point 5). Voltage Comparator The uncommitted voltage comparator (COMP2) can be used to monitor output voltages other than VOUTLO. Figure 8a shows how the comparator can be used to monitor a 12V supply (VOUTHI), while the 5V supply (VOUTLO) generates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull low. The FB pin is left floating. Figure 8b shows how the comparator can be used to monitor the 5V supply (VOUTHI) while the 3.3V supply (VOUTLO) generates a reset when it dips below 2.9V. When the 5V supply drops below 4.65V, COMPOUT will pull low. The FB pin is tied to VOUTLO.
5V 20 VCCLO 73.5k 20A 6 VCCLO COMP1 71.5k LTC1421 16 12V
FB
-
26.7k
11 10k 5% 15 107k 1% 13.7k 1%
+
20A 7 RESET TIMING COMP2
+ -
13
14 8
1421 F08a
1.232V
Figure 8a. Monitor 12V, Reset 5V at 4.65V
9
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
Figure 8c shows how the comparator can be used to generate a reset when the 12V supply (VOUTHI) drops below 10.8V. The 5V supply (VOUTLO) also generates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull the FB pin low setting the internal threshold voltage for comparator 1 to 5.88V. Since VOUTLO is less than 5.88V, PWRGD immediately goes low and a reset is generated 200ms later. Figure 8d shows how the comparator can be used to override the internal reset voltage for a 5V supply on VOUTLO.
3.3V 20 VCCLO 73.5k 20A 6 VCCLO COMP1 71.5k LTC1421 16 5V
-
26.7k
11
+
20A 7 RESET TIMING COMP2
15
+ -
13
14 8
1421 F08b
1.232V
Figure 8b. Monitor 5V, Reset 3.3V at 2.9V
VCCLO
5V 20 VCCLO 73.5k 20A 6 VCCLO COMP1 71.5k LTC1421 16 12V
-
26.7k
11
+
20A 7 RESET TIMING COMP2
15
+ -
13
14 8
1421 F08c
1.232V
Figure 8c. Reset 12V at 10.8V, Reset 5V at 4.65V
10
U
W
U
U
A 5k resistor is tied from the FB pin to VOUTLO, setting the internal threshold to about 2.9V. The new reset threshold voltage is set by the external resistive divider connected to COMP2. When VOUTLO drops below the new threshold, COMPOUT pulls FB to ground, changing the internal threshold at COMP1 to 5.88V and generating a reset. Finally, the comparator may be used to monitor a negative supply as shown in Figure 8e. The external resistor divider
5V 20 VCCLO 73.5k 20A 6 VCCLO COMP1 71.5k LTC1421 16 5k 5% 12V
-
26.7k
11
+
20A
10k 5% 107k 1% 38.3k 1%
15 COMP2
7 RESET TIMING
+ -
13
102k 1% 38.3k 1%
14 8
1421 F08d
1.232V
Figure 8d. Reset 5V at 4.5V
5V 20 LTC1421 73.5k 20A 6 VCCLO COMP1 71.5k 16 12V 10k 5%
-
26.7k
11
+
20A 7 RESET TIMING COMP2
15
+ -
13
107k 1% 13.7k 1%
14 8 13.7k 1%
1.232V
1421 F08e
107k 1% - 12V
Figure 8e. Monitor - 12V at - 10.8V, Reset 5V at 4.65V
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
is connected between REF (Pin 8) and the negative supply and the trip point of Comparator 2 set to GND. Soft Reset Generation A soft reset that doesn't cycle the supply voltage can be generated externally using Pin 11 (FB) as shown in Figure 9. For a 5V supply the FB pin is left floating to set the internal supply monitor trip voltage to 4.65V. However, if the FB pin is pulled to ground for more than 64s via a push button or open-collector logic gate, the internal trip point will go to 5.88V and the RESET pin will pull low. RESET will remain low for 200ms after the FB pin is released. The RESET signal will also be pulled low when the voltage at the VOUTLO pin dips below 4.65V for more than 32s. When using a 3.3V supply, a 1k resistor must be connected from the FB pin to VCCLO to set the internal trip point to 2.90V.
3.3V 1/6 LS7404 OPEN COLLECTOR R1 USED FOR 3.3V R1 SUPPLY ONLY 1k 11 7 FB RESET LTC1421 GND 12 5V
1421 F10
RESET LOGIC
64s FB RESET
200ms
1421 F09
Figure 9. Generating a Soft Reset
Undervoltage Lockout On power-up, an undervoltage lockout circuit prevents the GATELO and GATEHI charge pumps from turning on until VCCLO and VCCHI have both exceeded 2.45V. Electronic Circuit Breaker The LTC1421 features an electronic circuit breaker function that protects against short circuits or excessive currents on the supplies. By placing a sense resistor between the supply input and set pin of either supply, the circuit breaker will be tripped whenever the voltage across the
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sense resistor is greater than 50mV for more than 20s. When the circuit breaker trips, both N-channel MOSFETs are quickly turned off, FAULT and PWRGD go low and RESET is pulled low 32s later. FAULT can be connected to a LED or a logic signal back to the host to indicate a faulty board. The chip will remain in the tripped state until a power-on reset is generated, or the power on VCCHI and VCCLO is cycled. If the circuit breaker feature is not used, short VCCLO to SETLO and VCCHI to SETHI. If more than 20s of response time is needed to reject supply noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 10.
RSENSE CF 23 VCCLO RF 22 SETLO 21 GATELO LTC1421 20 VOUTLO Q1
Figure 10. Short-Circuit Protection Circuit
Auxiliary VCC When a short circuit occurs on the board, it is possible to draw enough current to cause the backplane supply voltage to collapse. If the input supply voltage collapses to a low enough voltage and the LTC1421 gate drive circuitry is unable to shut off the N-channel pass transistors, the system might freeze up in a permanent short condition. To prevent this from occurring, the gate discharge circuitry inside the LTC1421 is powered from AUXVCC, which is in turn powered from VCCLO through an internal Schottky diode and current limiting resistor (Figure 11).
VCCLO 23 10k 24 1F GATE DRIVE CIRCUITRY LTC1421
1421 F11
GATELO GATEHI 21 17
AUXVCC
Figure 11. AUXVCC Circuitry
11
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
CONNECTOR
When VCCLO collapses, there is enough energy stored on the 1F capacitor connected to AUXVCC to keep the gate discharge circuitry alive long enough to fully turn off the external N-channels. Power N-Channel Selection The RDS(ON) of the external pass transistor must be low enough so that the voltage drop across it is about 200mV or less at full current. If the RDS(ON) is too high, the voltage drop across the transistor might cause the output voltage to trip the reset circuit. Table 2 lists the transistors that are recommended for use with the LTC1421.
Table 2. N-Channel Selection Guide
CURRENT LEVEL (A) 0 to 1 1 to 2 2 to 5 PART NUMBER MMDF2N02E MMDF3NO2HD MTB30N06
MANUFACTURER Motorola Motorola Motorola
DESCRIPTION Dual N-Channel SO-8 RDS(ON) = 0.1 Dual N-Channel SO-8 RDS(ON) = 0.09 Single 30A N-Channel DD Pak RDS(ON) = 0.05 Single N-Channel DD Pak RDS(ON) = 0.025 Single N-Channel DD Pak RDS(ON) = 0.0095
SYSTEM DATA BUS
5 to 10
MTB50N06E
Motorola
CONNECTOR
10 to 20
MTB75N05HD
Motorola
Data Bus When a board is inserted or removed from the host, care must be given to prevent the system data bus from being corrupted when the data pins make or break contact. One problem is that the fully discharged input or output capacitance of the logic gates on the board will draw an inrush current when the data bus pins first make contact. The inrush current can temporarily corrupt the data bus, but usually will not cause long term damage. The problem can be minimized by insuring the input or output data bus capacitance is kept as small as possible. The second, and more serious problem involves the diodes to VCC at the input and output of most logic families (Figure 12).
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VCC D1 OUT D2 BOARD
1421 F12
DATA BUS
BACKPLANE
Figure 12. Typical Logic Gate Loading the Data Bus
R1 Q1 0.005 MTB50N06E 5V 23 22 21 20
+
VCC C4 2200F
LTC1421 5 DISABLE GND 12 QS3384 2 15 5 16 6 19 9 20 10 23 1 VCC 24 3 14 4 17 7 18 8 21 11 22 12 BOARD DATA BUS
GND
13
1421 F13
Figure 13: Buffering the Data Bus
With the board initially unpowered, the VCC input to the logic gate is at ground potential. When the data bus pins make contact, the bus line is clamped to ground through the input diode D1 to VCC. Large amounts of current can flow through the diode and cause the logic gate to latch up and destroy itself when the power is finally applied. This
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
can usually be prevented by using logic that does not include the clamping diodes such as the QSI 74FCTT family from Quality Semiconductor, or by using a data bus switch such as the 10-bit QS3384 QuickSwitch also from Quality Semiconductor (Tel: 408-450-8000). The QuickSwitch bus switch contains an N-channel placed in series with the data bus. The switch is turned off when the board is inserted and then enabled after the power is stable. The switch inputs and outputs do not have a parasitic diode back to VCC and have very low capacitance. The LTC1421 is designed to work directly with the QuickSwitch bus switch as shown in Figure 13. The DISABLE signal is connected to the enable pins of the QS3384, and each switch is placed in series with a data bus signal. When the board is inserted, the DISABLE
1 2 3 20ms 4 5 200ms
VCCLO
VCCHI
DISABLE CON1 CON2 CPON
GATEHI
VOUTHI
GATELO
VOUTLO PWRGD
RESET FAULT POR
1421 F14
Figure 14. Board Insertion Timing
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signal is pulled high, turning off the switches. After the board supply voltage ramps up and RESET goes high, DISABLE will pull low enabling the switches. Board Insertion Timing When the board is inserted, GND pin makes contact first, followed by VCCHI and VCCLO (Figure 14, time point 1). DISABLE is immediately pulled high, so the data bus switch is disabled. At the same time CON1 and CON2 make contact and are shorted to ground on the host side (time point 3). Since most boards need to be rocked back and forth to get them in place, there is a period of time when only one side of the connector is making contact. CON1 and CON2 should be located at opposite ends of the connector.
6
VTH1
13
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
When CON1 and CON2 are both forced to ground for more than 20ms, the LTC1421 assumes that the board is fully connected to the host and power-up can begin. When VCCLO and VCCHI exceed the 2.45V undervoltage lockout threshold, the 20A current reference is connected from RAMP to GND, the charge pumps are turned on and CPON is forced high (time point 4). VOUTHI and VOUTLO begin to ramp up. When VOUTLO exceeds the reset threshold voltage, PWRGD will immediately be forced high (time point 5). After a 200ms delay, RESET will be pulled high and DISABLE will be pulled low, enabling the data bus (time point 6). Ground Sense Comparator When POR is pulled low for more than 20ms, GATELO and GATEHI are pulled to ground and VOUTLO and VOUTHI will be discharged. If POR is pulled back high while VOUTLO and VOUTHI are still ramping down, the discharge will continue. When they drop below the VTRIP point, a powerup sequence will begin automatically. The trip point potential for LTC1421 is set at 0.1V and 2.5V for LTC1421-2.5. In applications, where either VOUTLO or VOUTHI might be forced above 100mV before power-up, the LTC1421-2.5 should be used. This could occur when leakage through the body diode of the logic chips keeps VOUTLO high or in the case where logic lines are precharged. In other applications, where outputs need to drop to near ground potential before ramping up again to ensure proper initial state for the logic chips, the LTC1421 should be used. Power-On Reset Timing The POR input is used to completely cycle the power supplies on the board or to reset the electronic circuit breaker feature. The POR pin can be connected to a grounded push button, toggle switch or a logic signal from the host. When POR is pulled low for more than 20ms, a power-on reset sequence begins (Figure 15,
1 VCCHI VCCLO DISABLE CON1 CON2 CPON
20ms
2
GATEHI
VOUTHI
GATELO
VOUTLO PWRGD RESET FAULT POR
Figure 15. Power-On Reset Timing
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3 32s
4
5
6
200ms
7
VTH2
VTH1
1421 F15
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
time point 2). Pulses less than 20ms on POR are ignored. CPON goes low. Both GATEHI and GATELO will be actively pulled down to GND. When VOUTLO drops below its reset threshold voltage, PWRGD will immediately pull low (time point 3) followed by RESET and DISABLE 32s later (time point 4). Both supplies will be discharged to ground and stay there until POR is pulled high. The circuit breaker can be reset by pulling POR low. After POR is low for more than 20ms, the chip will immediately try to power up the supplies. Circuit Breaker Timing The waveforms for the circuit when a short occurs on either supply during board insertion are shown in Figure 16. Time points 1 to 4 are the same as the board insertion example, but at time point 5, a short circuit is detected on one of the supplies. The charge pumps are immediately turned off, the outputs VOUTHI and VOUTLO are actively pulled to GND and the CPON and FAULT pins are pulled low. At time point 6, the circuit breaker is reset by pulling POR low. After POR has been low for 20ms (time point 7), CPON and FAULT are pulled high, the 20A reference current is connected to RAMP and the charge pumps are enabled. VOUTHI and VOUTLO ramp up at a controlled rate. When VOUTLO has exceeded its reset threshold, the PWRGD signal is pulled high (time point 8). After a 200ms delay, RESET is pulled high and DISABLE goes low.
1
2
3
20ms
VCCLO
VCCHI
DISABLE CON1 CON2 CPON
GATEHI
VOUTHI
GATELO VOUTLO
PWRGD
RESET
FAULT
POR
Figure 16. Circuit Breaker Timing
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5
6
20ms
7
8
200ms
9
VTH1
1421 F16
15
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
Board Removal Timing When the board is removed from the host, the sequence happens in reverse (Figure 17). Since CON1 and CON2 are the shortest pins, they break connection first and are internally pulled high (time point 1). The charge pumps are turned off, CPON is pulled low. VOUTLO and VOUTHI are actively pulled down. When VOUTLO falls below its reset threshold (time point 2) PWRGD is pulled low. To allow
1 2 32s VCCLO 3 4
VCCHI
DISABLE CON1 CON2 CPON
GATEHI
VOUTHI
GATELO VOUTLO
VTH2
PWRGD
RESET
FAULT
POR
1421 F17
Figure 17. Board Removal Timing
16
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time for power fail information to be stored in nonvolatile memory, the falling edge of RESET (time point 3) is delayed by 32s from the falling edged of PWRGD. Finally, the input supply pins VCCHI and VCCLO break contact (time point 4). If staggered pins are not used, the board may be powered down prior to removal by switching the POR pin to ground with a toggle switch.
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
5V Only Applications The LTC1421 may be used in 5V only applications as shown in Figure 18. A soft reset can be generated from the backplane via an open-collector inverter driving the FB (Pin 11) or by a push button to ground. A hard power reset is generated from the backplane via an open-collector inverter driving the POR (Pin 3). A hard reset cycles the power on the board or resets the electronic circuit breaker. The comparator is used to monitor the board supply voltage and will pull the POWERGOOD signal low as long as the supply remains above 4.65V. Note that a soft reset will not affect the POWERGOOD signal. The FAULT signal is also monitored to determine that the circuit breaker has tripped. - 48V and 24V Applications The LTC1421 may be used in - 48V applications as shown in Figure 19. The LTC1421 provides the hot insertion protection, while the 5V supply is generated by a power
5V C2 2200F 23 2 24 C1 1F 15 LTC1421 10k FAULT SOFT RESET 1/6 LS7004 HARD RESET
1421 F18
5V 10k POWERGOOD 5V
+
BACKPLANE
PC BOARD
Figure 18. 5V Only Application with Soft Reset
Q1 IRFR9110 R1 5k 1W D1 5V
- 48V
STAGGERED CONNECTOR
+
C2 2.2F 25V 2 24
23 22 21
- 48V
+
C1 1F 4 3 1
S1 12 - 48V - 48V BACKPLANE PC BOARD 5
1421 F19
Figure 19. - 48V to 5V Hot Swappable Supply
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R1 Q1 0.005 MTB50N06E 1W 5V
22
21 20 19 18 17 16 10 7 14 13 8 11
C2 1F R2 28k 1% LOGIC RESET R3 10.2k 1%
1 12 5 9 6 3 S1
1
+IN
+OUT
3
C3 2.2F 25V
+
R2 15k 1/8W R3 56k 1/2W Q2 MPSA06 R6 400 1/8W R5 10k 1/2W
2
ASTRODYNE ASD 10-48S5 -IN - OUT CONTROL 6
+
5
5V 2A C4 100F 16V
20 19 18 17 16 10 9 13 14 8 11 15 6 7 R4 300 1/8W
+
C4 100F 100V
LTC1421
17
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
module. The ground pin for the LTC1421 is connected to - 48V; Zener diode D1 and resistor R1 provide the positive supply for the chip. Bypass capacitor C4 is protected against inrush current by P-channel Q1. When the board is inserted into the backplane, transistor Q1 is turned off by resistor R2. When the connection sense pins, CON1 and CON2 have been connected to - 48V for more than 20ms, CPON pulls high turning on Q2 and the gate of Q1 starts to pull low with a time constant determined by R2, R3 and C3. At the same time, the voltage at the input to the power module starts to ramp up. When the voltage across the inputs to the power module reaches the comparator trip level set by R5 and R6, in this case - 32V, the comparator output pulls high and turns on the 5V supply. A cheaper solution is shown in Figure 20 using the LT(R)1170HV switcher. Again P-channel transistor Q1 protects the bypass capacitors against inrush current and resistors R5 and R6 set the comparator trip voltage. The LT1170HV is turned on via the VC pin. Resistors R11, R14 and transistor Q4 provide a monitoring path for the RESET signal which is level shifted up to 5V through an optoisolator. The P-channel power FET is being replaced by an N-channel FET in Figure 21 for the - 48V application. Again, Zener Diode D1 and resistor R1 provide the positive supply for the chip. Capacitor C1 is to insure Q1 stays off when the board is being hot inserted into the backplane. The resistor divider R1 and R2, along with the internal comparator, perform the undervoltage lock out function. Q1 would only be turned on when the input supply voltage is lower than - 42V. The power module would then be turned on by the optoisolator, 4N25, when the module's input voltage reaches 47V. Figure 22 shows how to use the LTC1421 with a 24V supply and a LT1074CT step-down switcher. Resistors R5 and R6 set the turn-on threshold to 22V. All of the supervisory signals can be used without level shifting. Figure 23 shows how to use the LTC1421 with a 5V supply and an LTC1430CS8 synchronous step-down switching regulator to generate 3.3V output at up to 10A for microprocessors. Resistors R4, R8 and R9 set the turn-on voltage at 4.8V and the turn-off at 4.25V. Pushbutton switch S1 provides users a way to reset the output while S2 is used to soft-reset the microprocessor only. Figure 24 shows how to use the LTC1421 with a 5V supply and a - 48V supply that is used to generate a 12V supply using a supply module. Resistors R3 and R4 are used to monitor the input voltage to the supply module. The module is prevented from turning on via the optoisolator until the input voltage reaches - 36V. Zener diode D2 prevents the CPON pin of the LTC1421 from being damaged by excessive voltage. Figure 25 shows how to use the LTC1421 to do overvoltage protection. Resistors R3 and R4 set the trip point at 7V. When the input supply voltage rises above 7V, Q2 is turned on and Q1 turned off while Q3 helps to discharge the output voltage. Figure 26 shows how to use the LTC1421 to control both the power-up and power-down sequence of the outputs. The 5V output would be powered up first followed by the 3V output. At power-down sequence, the 3V output would go down first followed by the 5V supply. Figure 27 shows how to use the LTC1421 to switch 3.3V, 5V, 12V and -12V supplies for PCI application. The rampup rate for 3.3V, 5V and 12V is determined by the ramp capacitor C2 while the -12V supply is controlled by R7 and C3. The internal comparator is being used to do the overcurrent protection for Q4 with the trip point set by resistors R6 and R8. The -12V supply does not have overcurrent protection. R10 is used to set the power good signal trip point at 10V. When the 12V output rises above 10V, the PCI controller gets a power good signal followed by RESET after 200ms.
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- 48V Q1 IRFR9110 L1 100H
+
R2 15k 1/8W
+ +
D2 7.5V 5 VCC SW LT1170HVCT 3 GND 1 FB VC 4 R10 4.32k 1/8W D4 Q3 Q4 MBR3100 2N5401 2N5401 C6 100F 100V C4 4.7F 50V
C3 2.2F 25V
D3 MBR3100 R11 4.32k 1/8W
APPLICATIONS INFORMATION
VCC 5V 3A
R1 5k 1W
C7 1000F 25V
C8 1000F 25V
+
23 22 21 20 19 18 17 16 R3 56k 1/2W Q2 MPSA06 R8 1k 1/8W R9 1k 1/8W C9 0.33F 50V R5 10k 1/2W
D1 5V
C2 2.2F 25V
+
C5 4.7F 50V
R12 10k 1/8W
- 48V 2 24 LTC1421 4 3 1 12 5 R6 400 1/8W
R4 10 300 9 1/8W
STAGGERED CONNECTOR
+
RESET
C1 1F
13 14 8 11 15 6 7
R13 1.24k 1/8W
R14 4.64k 1/8W
S1
- 48V
1421 F20
- 48V
BACKPLANE
PC BOARD
Figure 20. - 48V to 5V Hot Swappable Supply Using the LT1170HVCT
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LTC1421/LTC1421-2.5
+
+
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19
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
- 48V
5k 23 D1 4.3V 0.1F 24 12 0.1F 3 2 LTC1421 8 14 13 15 300 1N4148 0.1F 100 4N25 11 1 22 19 18 17 10k 4.5k 100F 5V 10A
STAGGERED CONNECTOR
- 48V
1421 F21
BACKPLANE
PC BOARD
Figure 21. - 48V to 5V Hot Swappable Supply
24V R1 5k 1/4W D1 5V C3 2.2F 25V
+
STAGGERED CONNECTOR
C2 2.2F 25V
23 22 21 20 19 18 17 16 R4 10 300 1/8W 9 13 14 8 11 15 6 7
+
2 24 C1 1F 4 3 1 LTC1421
FAULT POR S1
12
5
BACKPLANE
PC BOARD
Figure 22. 24V to 5V Hot Swappable Supply Using the LT1074CT
20
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+
VICOR VI-J30-CY
+
100F
-
GATE IN
-
Q1 IRFR9110
5
+
R2 15k 1/8W
+
VIN
VSW
4
L1 50H D4 MBR745 R7 2.8k 1% R8 2.21k 1%
C4 200F 50V 2
5V 5A
LT1074CT VC GND 3 FB 1
+
C5 500F 25V
R3 56k 1/8W Q2 MPSA06
R5 10k 1/2W
R6 620 1/8W R9 2.7k C6 0.01F
+
1421 F22
R2 0.01 5%,1W R1 0.005 5%,1W Q1 MTD20N03HL R9 26.7k 1%
5V
+ +
C5 10F 16V 7 G1 4 1 2 5 SHDN 6 VCC PVCC1 C6 0.1F 16V Q2 MTD20N03HL D1 1N4148
C3 220F 16V x4 R6 22 5% C4 0.1F 16V
APPLICATIONS INFORMATION W
2.7H 15A Q4 MTD20N03HL 3.3V 10A IMAX = 15A VCC P
R10 10k 5% R8 100k 1%
1 24 4 5 3 2 12 C8 220pF CERAMIC C7 4700pF CERAMIC LTC1421 FB COMP R7 3 8 GND G2 7.5k 5% LTC1430CS8 10 11
STAGGERED CONNECTOR
C2 0.1F R5 16V 510 5%
Q3 MTD20N03HL
+
S2 R4 10k 1% C10 1F 16V
6 7 8 14 13 15 9
C1 1F 16V
+
RESET GND
S1
C9 338F 10V x6
1421 F23
BACKPLANE
PC BOARD
S1: HARD POWER/CIRCUIT BREAKER RESET S2: SOFT RESET LTC1430 POWER-UP THRESHOLD: 4.8V ON 4.25V OFF
Figure 23. 5V to 3.3V Hot Swappable Supply Using the LTC1430CS8
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LTC1421/LTC1421-2.5
23 22 21 20 19 18 17 16
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21
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
5V R1 Q1 0.005 1W MTB50N06E 5V 8A
23
22
21
STAGGERED CONNECTOR
C1 1F 4 3 1 S1 12 FAULT
6
LTC1421
R3 340 1/8W R5 4.3k 1/8W Q3 2N5401
5
7
C3 0.47F - 48V
R6 15k 1/8W IRF530
R4 10k 1/8W
1421 F24
BACKPLANE
PC BOARD
Figure 24. 5V and - 48V to 12V Hot Swappable Supply
R1 0.005 Q1 1/2W MTB50N06E 5V 1k Q2 VN2222
STAGGERED CONNECTOR
12
100
Q3 VN2222 R3 47.5k
+
5V 8A 2200F 16V
23 22 21 20 19 18 17 16 1 24 10
C2 0.1F VCC P 7 8 14 13 15 R4 10k
1421 F25
+
C1 1F
3 2 12
LTC1421
RESET GND
S1
BACKPLANE
PC BOARD
Figure 25. Hot Swappable 5V Supply with Overvoltage Protection
22
+
2 24
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R7 1k 1/8W 20 19 18 17 16 10 9 13 14 8 11 15 6 C2 1F 1 C5 220F 100V
C4 2200F 16V +IN
+
+OUT
3
2
ASTRODYNE ASD10-48D12 -IN - OUT CONTROL
+
5
12V 0.42A C7 100F 16V -12V 0.42A C6 100F 16V
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
R2 0.005 1W 5V R1 0.005 Q1 1W MTB50N06E 3V R3 1M 5%,1/8W Q2 MTB50N06E
STAGGERED CONNECTOR
1 24
+
C1 1F 16V S1
4 5 3 2 12 LTC1421
BACKPLANE
PC BOARD
Figure 26. Power-Up and Power-Down Sequence Controller
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.318 - 0.328* (8.07 - 8.33) 24 23 22 21 20 19 18 17 16 15 14 13
0.205 - 0.212** (5.20 - 5.38)
0 - 8 0.301 - 0.311 (7.65 - 7.90) 0.002 - 0.008 (0.05 - 0.21)
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
0.0256 (0.65) BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SW Package 24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143) 24 23 22 21 0.598 - 0.614* (15.190 - 15.600) 20 19 18 17 16 15 14 13
0 - 8 TYP
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
0.050 (1.270) TYP
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.014 - 0.019 (0.356 - 0.482) TYP
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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+
0.047F
C4 2200F 16V
5V 8A
+
1k 23 22 21 20 19 18 17 16 10 11 6 7 8 14 13 15 9 C2 0.1F 24V
+
C5 0.1F 24V
C4 2200F 16V
3V 8A
R4 1k 5% 1/16W
R5 330k 5% 1/16W
VCC P RESET GND
R6 200k 5% 1/16W
1421 F26
0.068 - 0.078 (1.73 - 1.99)
0.010 - 0.015 (0.25 - 0.38)
1 2 3 4 5 6 7 8 9 10 11 12
G24 SSOP 0595
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
0.004 - 0.012 (0.102 - 0.305)
1
2
3
4
5
6
7
8
9
10
11
12
S24 (WIDE) 0996
23
LTC1421/LTC1421-2.5
TYPICAL APPLICATION
12V 500mA Q3 1/2 IRF7101 R2 0.015 5% 1W R10 100k R3 0.005 5% 1W PCI CONNECTOR 12V 3.3A CIRCUIT BREAKER Q4 IRF7413
3.3V 7.5A 5V 5A
R1 0.005 5% 1/2W 23 R14 5.1k 1 24 4 5 22
FAULT
ON/OFF PCI POWER CONTROLLER C1 1F 16V POWER GOOD RST # SELECT BITS BUS ENABLE DATA BUS
3 2
+
12
QuickSwitch R7 130k ALL RESISTORS 5%, 1/16W EXCEPT WHERE NOTED Q5 TP0610T R9 10 C3 1F 24V - 12V NO CIRCUIT BREAKER PCI PERIPHERAL
-12V 100mA MOTHERBOARD OR BACKPLANE
RELATED PARTS
PART NUMBER LTC1155 LTC1477/LTC1478 DESCRIPTION Dual High Side Switch Driver Single and Dual Protected High Side Switches COMMENTS Short-Circuit Protection and Micropower Standby Operation Inrush Current Limited, Built-In 2A Short-Circuit Protection
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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R4 30
R11 10
3.3V 11.5A CIRCUIT BREAKER 5V 10A CIRCUIT BREAKER
Q1 IRF7413 R12 10 21
20
19
18
17
16 10 11 6 7 8 14 13 15 9
C2 0.22F 24V R13 5.1k R6 100 1% 1/16W
LTC1421
R8 5.62k 1% 1/16W GND LOGIC RST #
R5 20k
Q2 1/2 IRF7101
1421 F27
Figure 27. PCI Power Controller
142125fa LT/TP 1098 2K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1996

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